MATLAB SIMULINK HDL CODER 1 Manual do Utilizador descarregar pdf (Página 9)

9/21/2011

1. Increase simulation speed

2. Simplify design entry, system test harness

A Few Ways to Reduce Development Time

creation, and exploration

3. Shorter iteration cycles required for RTL design

& verification

4. Integrate the separate workflows to facilitate

collaboration, re-use, and prototyping

Model-Based Design for Implementation

Algorithm Design

System Test Bench

RTL Design

Verification

MATLABMATLAB

® ®

andand SimulinkSimulink

®®

Algorithm and System DesignAlgorithm and System Design

Algorithm

Design

Fixed-Point

Timing / Control Logic

Architecture Exploration

Algorithms / IP

System

Test

Bench

Environment Models

Algorithms / IP

Analog Models

Digital Models

RTL

Design

IP Interfaces

Hardware Architecture

Verification

Functional Simulation

Static Timing Analysis

Timing Simulation

Behavioral Simulation

Back Annotation

Implement Design

Map

Synthesis

FPGA Requirements

Map

Place & Route

FPGA Hardware

Hardware Specification

Test Stimulus

1 2 3 4 5 6 7 8 9 10 11 12 13 14 ... 45 46

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