MATLAB SIMULINK HDL CODER 1 Manual do Utilizador descarregar pdf (Página 36)

9/21/2011

Digital Down Converter

 DDC acce

– A high sample-rate passband signal (may be 50 to 100 Msps)

 DDC produces

– A low sample-rate baseband signal ready for demodulation

~70 MSPS

~270 KSPS

Digital

Down

Converter

A/D

Conv

Section

Demod

Integrated HDL Verification

MATLABMATLAB

® ®

andand SimulinkSimulink

®®

Algorithm and System DesignAlgorithm and System Design

Model Refinement for HardwareModel Refinement for Hardware

Implement Design

Verification

Back Annotation

HDL CoHDL Co--SimulationSimulation

Automatic HDL Automatic HDL

Code GenerationCode Generation

Behavioral Simulation

Implement

Design

Map

Place & Route

Synthesis

Verification

Static Timing Analysis

Timing Simulation

Functional Simulation

FPGA HardwareFPGA Hardware

FPGAFPGA--inin--thethe--LoopLoop

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MATLAB SIMULINK HDL CODER 1 Manual do Utilizador Página 36