MATLAB SIMULINK HDL CODER 1 Manual do Utilizador descarregar pdf (Página 6)

9/21/2011

 Use Model-Based Design to provide

an integrated workflow

Things to remember ….

DESIGN

 Speed up algorithm development

with a unified design environment

 Automate manual steps in

FPGA implementation to enable

shorter iteration c

cles

Algorithm

Development

MATLAB

Simulink

Stateflow

 Integrate FPGA development tools to

reduce verification time

Agenda

9:45

Welcome

10:00

Reduce FPGA Develo

ment Time with Model-Based Desi

11:00

Break

11:15

Integrated HDL Verification

12:00

Xilinx Target-optimized FPGA Design Using MATLAB and Simulink

13:15

Lunch

13:15

Lunch

14:15

FPGA Design Optimization Techniques

15:45

Q&A, Summary and Wrap-up

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MATLAB SIMULINK HDL CODER 1 Manual do Utilizador Página 6