MATLAB SIMULINK HDL CODER 1 Manual do Utilizador descarregar pdf (Página 22)

9/21/2011

22

Hardware Design Challenges:

Speed Optimization

48

Finding the critical path in your model

can be challenging

Demo: HDL Workflow Advisor

>> Choose target workflow:

• FPGA-in-the-Loop

• FPGA Turnkey

• Design exploration:

Generic ASIC/FPGA

49

Choose FPGA target

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