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System Generator for DSPUser GuideUG640 (v 12.2) July 23, 2010

10 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Preface: About This GuideConventionsThis document uses the following

100 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorDesigns Using Stand

System Generator for DSP User Guide www.xilinx.com 101UG640 (v 12.2) July 23, 2010Design Styles for the DSP48For synthesis to work, the circuit must b

102 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System Generatormethod of generatin

System Generator for DSP User Guide www.xilinx.com 103UG640 (v 12.2) July 23, 2010Design Styles for the DSP48tree:.../sysgen/examples/dsp48/dsp48_macr

104 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorDSP48 Macro 2.0-Bas

System Generator for DSP User Guide www.xilinx.com 105UG640 (v 12.2) July 23, 2010Design Styles for the DSP484 inputs and 2 ouputs MUX circuit can be

106 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorYou can find the ab

System Generator for DSP User Guide www.xilinx.com 107UG640 (v 12.2) July 23, 2010Design Styles for the DSP488. Use RAMs, SRL16 to clock out control p

108 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorClock Enable Planni

System Generator for DSP User Guide www.xilinx.com 109UG640 (v 12.2) July 23, 2010Using FDATool in Digital Filter ApplicationsUsing FDATool in Digital

System Generator for DSP User Guide www.xilinx.com 11UG640 (v 12.2) July 23, 2010ConventionsConvention Meaning or Use ExampleBlue text Cross-reference

110 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorA demo included in

System Generator for DSP User Guide www.xilinx.com 111UG640 (v 12.2) July 23, 2010Using FDATool in Digital Filter Applicationscoefficients using the F

112 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorGenerate and Assign

System Generator for DSP User Guide www.xilinx.com 113UG640 (v 12.2) July 23, 2010Using FDATool in Digital Filter ApplicationsThe filter coefficients

114 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorBrowse Through and

System Generator for DSP User Guide www.xilinx.com 115UG640 (v 12.2) July 23, 2010Using FDATool in Digital Filter ApplicationsRun the Simulation1. Cha

116 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorIt is possible to i

System Generator for DSP User Guide www.xilinx.com 117UG640 (v 12.2) July 23, 2010Using FDATool in Digital Filter ApplicationsRestart the simulation a

118 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorGenerating Multiple

System Generator for DSP User Guide www.xilinx.com 119UG640 (v 12.2) July 23, 2010Generating Multiple Cycle-True Islands for Distinct Clocksrequiremen

12 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Preface: About This Guide

120 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorCrossing Clock Doma

System Generator for DSP User Guide www.xilinx.com 121UG640 (v 12.2) July 23, 2010Generating Multiple Cycle-True Islands for Distinct Clocksmember of

122 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorThe diagram below i

System Generator for DSP User Guide www.xilinx.com 123UG640 (v 12.2) July 23, 2010Generating Multiple Cycle-True Islands for Distinct ClocksThis is be

124 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System Generatorsubsystems to deter

System Generator for DSP User Guide www.xilinx.com 125UG640 (v 12.2) July 23, 2010Generating Multiple Cycle-True Islands for Distinct Clocks8. Press t

126 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorThere are several i

System Generator for DSP User Guide www.xilinx.com 127UG640 (v 12.2) July 23, 2010Generating Multiple Cycle-True Islands for Distinct Clocksuse unisim

128 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System Generatorlocked : out std_l

System Generator for DSP User Guide www.xilinx.com 129UG640 (v 12.2) July 23, 2010Generating Multiple Cycle-True Islands for Distinct Clocksclkfx =&g

System Generator for DSP User Guide www.xilinx.com 13UG640 (v 12.2) July 23, 2010Chapter 1Hardware Design Using System GeneratorSystem Generator is a

130 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorUsing ChipScope Pro

System Generator for DSP User Guide www.xilinx.com 131UG640 (v 12.2) July 23, 2010Using ChipScope Pro Analyzer for Real-Time Hardware Debugging3. The

132 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System Generator5. Integrate ChipSc

System Generator for DSP User Guide www.xilinx.com 133UG640 (v 12.2) July 23, 2010Using ChipScope Pro Analyzer for Real-Time Hardware DebuggingAfter p

134 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System Generator7. Connecting the C

System Generator for DSP User Guide www.xilinx.com 135UG640 (v 12.2) July 23, 2010Using ChipScope Pro Analyzer for Real-Time Hardware Debugging♦ Doubl

136 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System Generator1. Connect one end

System Generator for DSP User Guide www.xilinx.com 137UG640 (v 12.2) July 23, 2010Using ChipScope Pro Analyzer for Real-Time Hardware Debugging3. Conf

138 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorRe-capture the data

System Generator for DSP User Guide www.xilinx.com 139UG640 (v 12.2) July 23, 2010Using ChipScope Pro Analyzer for Real-Time Hardware DebuggingImporti

14 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorA Brief Introduction

140 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorTutorial Example: U

System Generator for DSP User Guide www.xilinx.com 141UG640 (v 12.2) July 23, 2010Using ChipScope Pro Analyzer for Real-Time Hardware DebuggingBenefit

142 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System Generator

System Generator for DSP User Guide www.xilinx.com 143UG640 (v 12.2) July 23, 2010Chapter 2Hardware/Software Co-DesignThe Chapter covers topics regard

144 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-DesignHardware/Software Co-Design in

System Generator for DSP User Guide www.xilinx.com 145UG640 (v 12.2) July 23, 2010Integrating a Processor with Custom LogicThe EDK Processor block pro

146 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-DesignMemory Map CreationA System Ge

System Generator for DSP User Guide www.xilinx.com 147UG640 (v 12.2) July 23, 2010Integrating a Processor with Custom LogicHardware GenerationThe EDK

148 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-DesignCo-Simulation block, these por

System Generator for DSP User Guide www.xilinx.com 149UG640 (v 12.2) July 23, 2010Integrating a Processor with Custom LogicAs shown in the following f

System Generator for DSP User Guide www.xilinx.com 15UG640 (v 12.2) July 23, 2010A Brief Introduction to FPGAsMHz are common today) and a highly-distr

150 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-DesignNote: If you launch Xilinx SDK

System Generator for DSP User Guide www.xilinx.com 151UG640 (v 12.2) July 23, 2010Integrating a Processor with Custom LogicThere is a Shared Memory Se

152 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-Design// obtain the memory location

System Generator for DSP User Guide www.xilinx.com 153UG640 (v 12.2) July 23, 2010Integrating a Processor with Custom LogicSingle-Word ReadsThe follow

154 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-DesignAsynchronous SupportAsynchrono

System Generator for DSP User Guide www.xilinx.com 155UG640 (v 12.2) July 23, 2010Integrating a Processor with Custom LogicIn hardware co-simulation,

156 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-DesignAs a rule of thumb, if you wan

System Generator for DSP User Guide www.xilinx.com 157UG640 (v 12.2) July 23, 2010Integrating a Processor with Custom LogicThe third advantage is that

158 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-Design4. Change the input clock freq

System Generator for DSP User Guide www.xilinx.com 159UG640 (v 12.2) July 23, 2010Integrating a Processor with Custom LogicWhen a System Generator mod

16 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System Generatorlogic abstractions t

160 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-DesignPORT fpga_0_clk_1_sys_clk_pin

System Generator for DSP User Guide www.xilinx.com 161UG640 (v 12.2) July 23, 2010Integrating a Processor with Custom Logic4. Comment out the software

162 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-DesignStarter board). You have to re

System Generator for DSP User Guide www.xilinx.com 163UG640 (v 12.2) July 23, 2010EDK SupportEDK SupportImporting an EDK ProcessorNote: Starting with

164 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-DesignEDK Import WizardWhen the Wiza

System Generator for DSP User Guide www.xilinx.com 165UG640 (v 12.2) July 23, 2010EDK SupportExposing Processor Ports to System GeneratorThe preferred

166 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-DesignExporting a pcoreSystem Genera

System Generator for DSP User Guide www.xilinx.com 167UG640 (v 12.2) July 23, 2010Designing with Embedded Processors and MicrocontrollersArchitecture

168 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-DesignALUThe Arithmetic Logic Unit (

System Generator for DSP User Guide www.xilinx.com 169UG640 (v 12.2) July 23, 2010Designing with Embedded Processors and Microcontrollersb. Double-cli

System Generator for DSP User Guide www.xilinx.com 17UG640 (v 12.2) July 23, 2010A Brief Introduction to FPGAsdivision multiplexed (TDM) data streams.

170 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-Designd. Double-click the PicoBlaze

System Generator for DSP User Guide www.xilinx.com 171UG640 (v 12.2) July 23, 2010Designing with Embedded Processors and MicrocontrollersClick on the

172 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-DesignOutput should look like this:N

System Generator for DSP User Guide www.xilinx.com 173UG640 (v 12.2) July 23, 2010Designing with Embedded Processors and MicrocontrollersDesigning and

174 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-Design2. Prepare to export the pcore

System Generator for DSP User Guide www.xilinx.com 175UG640 (v 12.2) July 23, 2010Designing with Embedded Processors and Microcontrollersthe EDK Expor

176 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-DesignWrite SoftwareCreate a new sof

System Generator for DSP User Guide www.xilinx.com 177UG640 (v 12.2) July 23, 2010Designing with Embedded Processors and MicrocontrollersThere can be

178 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-DesignTutorial Example - Designing a

System Generator for DSP User Guide www.xilinx.com 179UG640 (v 12.2) July 23, 2010Designing with Embedded Processors and MicrocontrollersCreate an XPS

18 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System Generatorhave detailed knowle

180 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-DesignImport the XPS Project In this

System Generator for DSP User Guide www.xilinx.com 181UG640 (v 12.2) July 23, 2010Designing with Embedded Processors and MicrocontrollersConfigure Mem

182 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-Designcorresponding device software

System Generator for DSP User Guide www.xilinx.com 183UG640 (v 12.2) July 23, 2010Designing with Embedded Processors and MicrocontrollersYou can then

184 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-DesignCreate a Testbench ModelA test

System Generator for DSP User Guide www.xilinx.com 185UG640 (v 12.2) July 23, 2010Designing with Embedded Processors and MicrocontrollersUpdate the Co

186 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-Design•Flow control = noneSet the si

System Generator for DSP User Guide www.xilinx.com 187UG640 (v 12.2) July 23, 2010Designing with Embedded Processors and Microcontrollers4. Next, tell

188 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-Design7. Base System Builder – Confi

System Generator for DSP User Guide www.xilinx.com 189UG640 (v 12.2) July 23, 2010Designing with Embedded Processors and MicrocontrollersAdding a New

System Generator for DSP User Guide www.xilinx.com 19UG640 (v 12.2) July 23, 2010Design Flows using System GeneratorAlgorithm ExplorationSystem Genera

190 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-Design5. Next, create Source or head

System Generator for DSP User Guide www.xilinx.com 191UG640 (v 12.2) July 23, 2010Designing with Embedded Processors and MicrocontrollersUsing Platfor

192 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-DesignCreating a Hello World Applica

System Generator for DSP User Guide www.xilinx.com 193UG640 (v 12.2) July 23, 2010Designing with Embedded Processors and MicrocontrollersGetting help

194 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-DesignHow to Migrate to the Standalo

System Generator for DSP User Guide www.xilinx.com 195UG640 (v 12.2) July 23, 2010Designing with Embedded Processors and Microcontrollers2. Click OK t

196 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-Design3. Right-click on the system.x

System Generator for DSP User Guide www.xilinx.com 197UG640 (v 12.2) July 23, 2010Designing with Embedded Processors and Microcontrollers5. Enter the

198 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-Design6. Right-click on SysGen_VFBC

System Generator for DSP User Guide www.xilinx.com 199UG640 (v 12.2) July 23, 2010Designing with Embedded Processors and Microcontrollers7. Enter the

System Generator for DSP User Guide www.xilinx.com UG640 (v 12.2) July 23, 2010Xilinx is disclosing this user guide, manual, release note, and/or spec

20 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorSystem-Level Modelin

200 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-Design8. The last step is to either

System Generator for DSP User Guide www.xilinx.com 201UG640 (v 12.2) July 23, 2010Designing with Embedded Processors and MicrocontrollersThe following

202 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-DesignDesign DescriptionThe System G

System Generator for DSP User Guide www.xilinx.com 203UG640 (v 12.2) July 23, 2010Designing with Embedded Processors and MicrocontrollersThe two desig

204 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-Designwant to bring the MicroBlaze p

System Generator for DSP User Guide www.xilinx.com 205UG640 (v 12.2) July 23, 2010Designing with Embedded Processors and MicrocontrollersStep 2 Genera

206 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-Design6. Select the Spartan-6 SP601

System Generator for DSP User Guide www.xilinx.com 207UG640 (v 12.2) July 23, 2010Designing with Embedded Processors and Microcontrollers9. Use the Re

208 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-Design2. Double-click on the MicroBl

System Generator for DSP User Guide www.xilinx.com 209UG640 (v 12.2) July 23, 2010Designing with Embedded Processors and Microcontrollers6. Click Add

System Generator for DSP User Guide www.xilinx.com 21UG640 (v 12.2) July 23, 2010System-Level Modeling in System GeneratorSystem Generator BlocksetsA

210 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-Design9. You are now ready to genera

System Generator for DSP User Guide www.xilinx.com 211UG640 (v 12.2) July 23, 2010Designing with Embedded Processors and Microcontrollers1. Delete the

212 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-Design4. Double click on the Subsyst

System Generator for DSP User Guide www.xilinx.com 213UG640 (v 12.2) July 23, 2010Designing with Embedded Processors and MicrocontrollersNote: When SD

214 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-Design6. Continuing from step 5, cre

System Generator for DSP User Guide www.xilinx.com 215UG640 (v 12.2) July 23, 2010Designing with Embedded Processors and MicrocontrollersNote: Notice

216 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-Designc. View the Silicon Labs CP210

System Generator for DSP User Guide www.xilinx.com 217UG640 (v 12.2) July 23, 2010Designing with Embedded Processors and Microcontrollersb. Expand the

218 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-DesignThe tool should start download

System Generator for DSP User Guide www.xilinx.com 219UG640 (v 12.2) July 23, 2010Designing with Embedded Processors and MicrocontrollersNote: Here ar

22 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorXilinx BlocksetThe X

220 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-Design15. First, just download the b

System Generator for DSP User Guide www.xilinx.com 221UG640 (v 12.2) July 23, 2010Designing with Embedded Processors and Microcontrollers18. Instead o

222 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-Design22. Next, terminate the curren

System Generator for DSP User Guide www.xilinx.com 223UG640 (v 12.2) July 23, 2010Designing with Embedded Processors and MicrocontrollersSummaryThe fo

224 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 2: Hardware/Software Co-Design

System Generator for DSP User Guide www.xilinx.com 225UG640 (v 12.2) July 23, 2010Chapter 3Using Hardware Co-SimulationIntroductionSystem Generator pr

226 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 3: Using Hardware Co-SimulationJTAG-Based Hardware Co-Simula

System Generator for DSP User Guide www.xilinx.com 227UG640 (v 12.2) July 23, 2010Compiling a Model for Hardware Co-SimulationCompiling a Model for Ha

228 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 3: Using Hardware Co-SimulationNote: A status dialog box (sh

System Generator for DSP User Guide www.xilinx.com 229UG640 (v 12.2) July 23, 2010Hardware Co-Simulation Blocksout of the library and use it in your S

System Generator for DSP User Guide www.xilinx.com 23UG640 (v 12.2) July 23, 2010System-Level Modeling in System Generatordescription of its implement

230 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 3: Using Hardware Co-Simulationother System Generator blocks

System Generator for DSP User Guide www.xilinx.com 231UG640 (v 12.2) July 23, 2010Hardware Co-Simulation ClockingHardware Co-Simulation ClockingSelect

232 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 3: Using Hardware Co-SimulationClocking ModesThere are sever

System Generator for DSP User Guide www.xilinx.com 233UG640 (v 12.2) July 23, 2010Board-Specific I/O PortsNote: The clocking options available to a ha

234 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 3: Using Hardware Co-SimulationGenerator compiles the design

System Generator for DSP User Guide www.xilinx.com 235UG640 (v 12.2) July 23, 2010Ethernet Hardware Co-SimulationPoint-to-Point Ethernet Hardware Co-S

236 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 3: Using Hardware Co-Simulation2. Use the Configuration tab

System Generator for DSP User Guide www.xilinx.com 237UG640 (v 12.2) July 23, 2010Ethernet Hardware Co-Simulation3. Use the Ethernet tab to configure

238 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 3: Using Hardware Co-SimulationNote: The MAC address must be

System Generator for DSP User Guide www.xilinx.com 239UG640 (v 12.2) July 23, 2010Ethernet Hardware Co-SimulationKnown Issues• If you encounter proble

24 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorIn the System Genera

240 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 3: Using Hardware Co-SimulationRemote JTAG Cable Support in

System Generator for DSP User Guide www.xilinx.com 241UG640 (v 12.2) July 23, 2010Ethernet Hardware Co-SimulationIf the Cable Location is set to Remot

242 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 3: Using Hardware Co-SimulationShared Memory SupportSystem G

System Generator for DSP User Guide www.xilinx.com 243UG640 (v 12.2) July 23, 2010Shared Memory SupportCompiling Shared Memories for Hardware Co-Simul

244 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 3: Using Hardware Co-SimulationNote: The name of the hardwar

System Generator for DSP User Guide www.xilinx.com 245UG640 (v 12.2) July 23, 2010Shared Memory SupportViewing Shared Memory InformationHardware co-si

246 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 3: Using Hardware Co-SimulationWhen software shared memory o

System Generator for DSP User Guide www.xilinx.com 247UG640 (v 12.2) July 23, 2010Shared Memory Supportshared memories include additional logic to han

248 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 3: Using Hardware Co-SimulationSystem Generator performs hig

System Generator for DSP User Guide www.xilinx.com 249UG640 (v 12.2) July 23, 2010Shared Memory Supportis possible for the PC to write to the register

System Generator for DSP User Guide www.xilinx.com 25UG640 (v 12.2) July 23, 2010System-Level Modeling in System GeneratorSimulink scope), but does no

250 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 3: Using Hardware Co-SimulationAsynchronous FIFOs are typica

System Generator for DSP User Guide www.xilinx.com 251UG640 (v 12.2) July 23, 2010Shared Memory SupportFIFO block in user design. The read side of the

252 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 3: Using Hardware Co-SimulationNote: You may find the names

System Generator for DSP User Guide www.xilinx.com 253UG640 (v 12.2) July 23, 2010Specifying Xilinx Tool Flow SettingsThe Hardware Co-Simulation Setti

254 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 3: Using Hardware Co-SimulationFrame-Based Acceleration usin

System Generator for DSP User Guide www.xilinx.com 255UG640 (v 12.2) July 23, 2010Frame-Based Acceleration using Hardware Co-Simulationbuffers is limi

256 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 3: Using Hardware Co-Simulationco-simulation, you create emb

System Generator for DSP User Guide www.xilinx.com 257UG640 (v 12.2) July 23, 2010Frame-Based Acceleration using Hardware Co-Simulationavailable in th

258 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 3: Using Hardware Co-Simulationcompiled into the FPGA for ha

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26 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorHardware Oversamplin

260 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 3: Using Hardware Co-SimulationCompiling for Hardware Co-sim

System Generator for DSP User Guide www.xilinx.com 261UG640 (v 12.2) July 23, 2010Frame-Based Acceleration using Hardware Co-Simulationmemory informat

262 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 3: Using Hardware Co-Simulation15. Record the amount of time

System Generator for DSP User Guide www.xilinx.com 263UG640 (v 12.2) July 23, 2010Frame-Based Acceleration using Hardware Co-Simulation17. Open macfir

264 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 3: Using Hardware Co-Simulation19. On the parameters dialog

System Generator for DSP User Guide www.xilinx.com 265UG640 (v 12.2) July 23, 2010Frame-Based Acceleration using Hardware Co-Simulation21. Add the har

266 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 3: Using Hardware Co-SimulationThe simulation flow of data t

System Generator for DSP User Guide www.xilinx.com 267UG640 (v 12.2) July 23, 2010Real-Time Signal Processing using Hardware Co-SimulationReal-Time Si

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System Generator for DSP User Guide www.xilinx.com 269UG640 (v 12.2) July 23, 2010Real-Time Signal Processing using Hardware Co-SimulationNote: The ou

System Generator for DSP User Guide www.xilinx.com 27UG640 (v 12.2) July 23, 2010System-Level Modeling in System GeneratorThe Clock Enables OptionWhen

270 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 3: Using Hardware Co-Simulation128. If you decide to process

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272 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 3: Using Hardware Co-SimulationOnce the dialog box is open,

System Generator for DSP User Guide www.xilinx.com 273UG640 (v 12.2) July 23, 2010Real-Time Signal Processing using Hardware Co-Simulationlock of Foo

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28 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorA dcm_reset input po

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System Generator for DSP User Guide www.xilinx.com 283UG640 (v 12.2) July 23, 2010Installing Your Board for Ethernet Hardware Co-SimulationNote: The C

284 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 3: Using Hardware Co-SimulationAs shown below, set the Confi

System Generator for DSP User Guide www.xilinx.com 285UG640 (v 12.2) July 23, 2010Installing Your Board for Ethernet Hardware Co-Simulationc. To ensur

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System Generator for DSP User Guide www.xilinx.com 287UG640 (v 12.2) July 23, 2010Installing Your Board for Ethernet Hardware Co-SimulationSetup the M

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System Generator for DSP User Guide www.xilinx.com 29UG640 (v 12.2) July 23, 2010System-Level Modeling in System Generator• Addressable Shift Register

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System Generator for DSP User Guide www.xilinx.com 295UG640 (v 12.2) July 23, 2010Installing Your Board for Ethernet Hardware Co-SimulationSetup the S

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System Generator for DSP User Guide www.xilinx.com 3UG640 (v 12.2) July 23, 2010Preface: About This GuideGuide Contents . . . . . . . . . . . . . . .

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302 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 3: Using Hardware Co-Simulation1. Position the ML402 board s

System Generator for DSP User Guide www.xilinx.com 303UG640 (v 12.2) July 23, 2010Installing Your Board for JTAG Hardware Co-SimulationInstalling an M

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System Generator for DSP User Guide www.xilinx.com 307UG640 (v 12.2) July 23, 2010Supporting New Boards through JTAG Hardware Co-SimulationSupporting

308 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 3: Using Hardware Co-SimulationSBDBuilder Dialog BoxAfter in

System Generator for DSP User Guide www.xilinx.com 309UG640 (v 12.2) July 23, 2010Supporting New Boards through JTAG Hardware Co-Simulation• Frequency

System Generator for DSP User Guide www.xilinx.com 31UG640 (v 12.2) July 23, 2010System-Level Modeling in System Generatora. Double-click on the file

310 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 3: Using Hardware Co-Simulation• Add: Brings up the dialog t

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System Generator for DSP User Guide www.xilinx.com 313UG640 (v 12.2) July 23, 2010Supporting New Boards through JTAG Hardware Co-SimulationBoard Suppo

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System Generator for DSP User Guide www.xilinx.com 315UG640 (v 12.2) July 23, 2010Supporting New Boards through JTAG Hardware Co-SimulationOnce you ha

316 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 3: Using Hardware Co-SimulationManual Specification of Board

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System Generator for DSP User Guide www.xilinx.com 319UG640 (v 12.2) July 23, 2010Supporting New Boards through JTAG Hardware Co-Simulationor director

32 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorThis design is compr

320 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 3: Using Hardware Co-Simulation

System Generator for DSP User Guide www.xilinx.com 321UG640 (v 12.2) July 23, 2010Chapter 4Importing HDL ModulesSometimes it is important to add one o

322 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 4: Importing HDL ModulesBlack Box HDL Requirements and Restr

System Generator for DSP User Guide www.xilinx.com 323UG640 (v 12.2) July 23, 2010Black Box Configuration Wizard• The name of a clock enable must be t

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System Generator for DSP User Guide www.xilinx.com 325UG640 (v 12.2) July 23, 2010Black Box Configuration M-Function• Port descriptions; • Generics re

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System Generator for DSP User Guide www.xilinx.com 327UG640 (v 12.2) July 23, 2010Black Box Configuration M-Functionaccessing the port objects that ar

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System Generator for DSP User Guide www.xilinx.com 333UG640 (v 12.2) July 23, 2010Black Box Configuration M-FunctionaddGeneric(identifier, value) Defi

334 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 4: Importing HDL ModulesSysgenPortDescriptor Member Variable

System Generator for DSP User Guide www.xilinx.com 335UG640 (v 12.2) July 23, 2010HDL Co-SimulationHDL Co-SimulationIntroductionThis topic describes h

336 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 4: Importing HDL ModulesModelSim SimulatorTo use the ModelSi

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System Generator for DSP User Guide www.xilinx.com 341UG640 (v 12.2) July 23, 2010Black Box Examples

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System Generator for DSP User Guide www.xilinx.com 37UG640 (v 12.2) July 23, 2010System-Level Modeling in System GeneratorNaNs that drive a Gateway In

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376 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 4: Importing HDL Modulesb. Set the appropriate bit width for

System Generator for DSP User Guide www.xilinx.com 377UG640 (v 12.2) July 23, 2010Chapter 5System Generator Compilation TypesThere are different ways

378 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 5: System Generator Compilation TypesHDL Netlist Compilation

System Generator for DSP User Guide www.xilinx.com 379UG640 (v 12.2) July 23, 2010Bitstream CompilationAs shown below, you may select the NGC compilat

38 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorAs shown below, in t

380 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 5: System Generator Compilation TypesAs shown below, you may

System Generator for DSP User Guide www.xilinx.com 381UG640 (v 12.2) July 23, 2010Bitstream CompilationAdditional SettingsYou may access additional co

382 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 5: System Generator Compilation TypesRe-Compiling EDK Proces

System Generator for DSP User Guide www.xilinx.com 383UG640 (v 12.2) July 23, 2010EDK Export ToolEDK Export ToolThe EDK Export Tool allows a System Ge

384 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 5: System Generator Compilation TypesCreating a Custom Bus I

System Generator for DSP User Guide www.xilinx.com 385UG640 (v 12.2) July 23, 2010EDK Export ToolIn another model (shown below), you create correspond

386 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 5: System Generator Compilation TypesThe following table sho

System Generator for DSP User Guide www.xilinx.com 387UG640 (v 12.2) July 23, 2010Hardware Co-Simulation CompilationHardware Co-Simulation Compilation

388 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 5: System Generator Compilation TypesAfter filling out the d

System Generator for DSP User Guide www.xilinx.com 389UG640 (v 12.2) July 23, 2010Timing and Power Analysis CompilationTiming Analysis Concepts Review

System Generator for DSP User Guide www.xilinx.com 39UG640 (v 12.2) July 23, 2010Automatic Code GenerationResource EstimationSystem Generator supplies

390 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 5: System Generator Compilation TypesClock Skew and JitterTh

System Generator for DSP User Guide www.xilinx.com 391UG640 (v 12.2) July 23, 2010Timing and Power Analysis Compilation• Levels of Logic: The number o

392 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 5: System Generator Compilation Typessource and parity_reg a

System Generator for DSP User Guide www.xilinx.com 393UG640 (v 12.2) July 23, 2010Timing and Power Analysis CompilationThe histogram will quickly give

394 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 5: System Generator Compilation TypesHistogram DetailThe sli

System Generator for DSP User Guide www.xilinx.com 395UG640 (v 12.2) July 23, 2010Timing and Power Analysis Compilationabout every net and logic delay

396 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 5: System Generator Compilation Typesf. Using Hard Cores. Ar

System Generator for DSP User Guide www.xilinx.com 397UG640 (v 12.2) July 23, 2010Timing and Power Analysis CompilationTutorial Example: Using the Tim

398 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 5: System Generator Compilation TypesGenerate the Example De

System Generator for DSP User Guide www.xilinx.com 399UG640 (v 12.2) July 23, 2010Timing and Power Analysis CompilationThere are two failing paths, no

4 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010A Step-by-Step Example . . . . . . . . . . . . . . . . . . . . . . . .

40 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorCompiling and Simula

400 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 5: System Generator Compilation TypesThis will add a registe

System Generator for DSP User Guide www.xilinx.com 401UG640 (v 12.2) July 23, 2010Creating Compilation TargetsExcellent! No more failing paths! The de

402 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 5: System Generator Compilation Typeswith it. New compilatio

System Generator for DSP User Guide www.xilinx.com 403UG640 (v 12.2) July 23, 2010Creating Compilation Targets1. The name of the compilation target as

404 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 5: System Generator Compilation Typesdescription of the desi

System Generator for DSP User Guide www.xilinx.com 405UG640 (v 12.2) July 23, 2010Creating Compilation Targets5. Create a new directory (e.g., Bitstre

406 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 5: System Generator Compilation Types

System Generator for DSP User Guide www.xilinx.com 407UG640 (v 12.2) July 23, 2010AAddressable Shift Register block 17Algorithm Exploration 19ASR bl

408 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010DCM reset pin 42Debuggingusing ChipScope Pro 130Defining New Compi

System Generator for DSP User Guide www.xilinx.com 409UG640 (v 12.2) July 23, 2010Installing an SP601/SP605 Board for Ethernet Hardware Co-Sim 299Ins

System Generator for DSP User Guide www.xilinx.com 41UG640 (v 12.2) July 23, 2010Automatic Code GenerationCompilation Type and the Generate ButtonPres

410 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010adding a block to a Configurable Subsystem 86and Configurable Subsy

42 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorSynthesis tool Speci

System Generator for DSP User Guide www.xilinx.com 43UG640 (v 12.2) July 23, 2010Automatic Code GenerationSimulink System PeriodYou must specify a val

44 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorHierarchical Control

System Generator for DSP User Guide www.xilinx.com 45UG640 (v 12.2) July 23, 2010Automatic Code Generationno testbench is requested, then the key file

46 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorUsing the System Gen

System Generator for DSP User Guide www.xilinx.com 47UG640 (v 12.2) July 23, 2010Automatic Code GenerationConstraints ExampleThe figure below shows a

48 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorGroup to group const

System Generator for DSP User Guide www.xilinx.com 49UG640 (v 12.2) July 23, 2010Automatic Code Generationadded to a larger design, but the clock wrap

System Generator for DSP User Guide www.xilinx.com 5UG640 (v 12.2) July 23, 2010EDK Processor Block . . . . . . . . . . . . . . . . . . . . . . . . .

50 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorThe “Expose Clock Po

System Generator for DSP User Guide www.xilinx.com 51UG640 (v 12.2) July 23, 2010Compiling MATLAB into an FPGACompiling MATLAB into an FPGASystem Gene

52 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System Generatorelsez = y;end The xl

System Generator for DSP User Guide www.xilinx.com 53UG640 (v 12.2) July 23, 2010Compiling MATLAB into an FPGA% supported by the Xilinx MCode block. T

54 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorAfter setting the di

System Generator for DSP User Guide www.xilinx.com 55UG640 (v 12.2) July 23, 2010Compiling MATLAB into an FPGAM-functions using Xilinx data types and

56 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorShift OperationsThis

System Generator for DSP User Guide www.xilinx.com 57UG640 (v 12.2) July 23, 2010Compiling MATLAB into an FPGAPassing Parameters into the MCode BlockT

58 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorTo pass parameters t

System Generator for DSP User Guide www.xilinx.com 59UG640 (v 12.2) July 23, 2010Compiling MATLAB into an FPGAThe above interface window sets the M-fu

6 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Restrictions on Shared Memories . . . . . . . . . . . . . . . . . . .

60 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorOptional Input Ports

System Generator for DSP User Guide www.xilinx.com 61UG640 (v 12.2) July 23, 2010Compiling MATLAB into an FPGAThe Block Interface Editor of the MCode

62 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorFinite State Machine

System Generator for DSP User Guide www.xilinx.com 63UG640 (v 12.2) July 23, 2010Compiling MATLAB into an FPGAstate = seen_10;endcase seen_10 % seen 1

64 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System Generatorendelseif ~enelse% i

System Generator for DSP User Guide www.xilinx.com 65UG640 (v 12.2) July 23, 2010Compiling MATLAB into an FPGAOptional inputs rst and load of block Ac

66 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorThe example contains

System Generator for DSP User Guide www.xilinx.com 67UG640 (v 12.2) July 23, 2010Compiling MATLAB into an FPGAerror('latency must be at least 1&a

68 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorIn order to verify t

System Generator for DSP User Guide www.xilinx.com 69UG640 (v 12.2) July 23, 2010Compiling MATLAB into an FPGARPN CalculatorThis example shows how to

System Generator for DSP User Guide www.xilinx.com 7UG640 (v 12.2) July 23, 2010Chapter 5: System Generator Compilation TypesHDL Netlist Compilation

70 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorOP_DROP = 6;q = acc;

System Generator for DSP User Guide www.xilinx.com 71UG640 (v 12.2) July 23, 2010Compiling MATLAB into an FPGAExample of disp FunctionThe following MC

72 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorHere are the lines t

System Generator for DSP User Guide www.xilinx.com 73UG640 (v 12.2) July 23, 2010Importing a System Generator Design into a Bigger SystemImporting a S

74 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorNew Integration Flow

System Generator for DSP User Guide www.xilinx.com 75UG640 (v 12.2) July 23, 2010Importing a System Generator Design into a Bigger SystemA Step-by-Ste

76 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorGenerating the HDL F

System Generator for DSP User Guide www.xilinx.com 77UG640 (v 12.2) July 23, 2010Importing a System Generator Design into a Bigger SystemThe transcrip

78 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System Generator3. Repeat item 2 wit

System Generator for DSP User Guide www.xilinx.com 79UG640 (v 12.2) July 23, 2010Importing a System Generator Design into a Bigger System4. As shown b

8 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010

80 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System Generator• The ce16_c4b7e244_

System Generator for DSP User Guide www.xilinx.com 81UG640 (v 12.2) July 23, 2010Importing a System Generator Design into a Bigger System3. In the Pro

82 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorThe previous screen

System Generator for DSP User Guide www.xilinx.com 83UG640 (v 12.2) July 23, 2010Configurable Subsystems and System GeneratorConfigurable Subsystems a

84 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System Generator• Drag a template bl

System Generator for DSP User Guide www.xilinx.com 85UG640 (v 12.2) July 23, 2010Configurable Subsystems and System GeneratorUsing a Configurable Subs

86 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorDeleting a Block fro

System Generator for DSP User Guide www.xilinx.com 87UG640 (v 12.2) July 23, 2010Configurable Subsystems and System Generator• Double click on the tem

88 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System Generator• Drag a manager blo

System Generator for DSP User Guide www.xilinx.com 89UG640 (v 12.2) July 23, 2010Notes for Higher Performance FPGA DesignNotes for Higher Performance

System Generator for DSP User Guide www.xilinx.com 9UG640 (v 12.2) July 23, 2010PrefaceAbout This GuideThis User Guide provides in-depth discussions o

90 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorReduce the Clock Ena

System Generator for DSP User Guide www.xilinx.com 91UG640 (v 12.2) July 23, 2010Processing a System Generator Design with FPGA Physical Design ToolsS

92 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorIn the Project Navig

System Generator for DSP User Guide www.xilinx.com 93UG640 (v 12.2) July 23, 2010Processing a System Generator Design with FPGA Physical Design ToolsT

94 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorCustomizing your Sys

System Generator for DSP User Guide www.xilinx.com 95UG640 (v 12.2) July 23, 2010Processing a System Generator Design with FPGA Physical Design Toolsm

96 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System GeneratorResetting Auto-Gener

System Generator for DSP User Guide www.xilinx.com 97UG640 (v 12.2) July 23, 2010Resetting Auto-Generated Clock Enable LogicTable 1-1:Block NameSynchr

98 www.xilinx.com System Generator for DSP User GuideUG640 (v 12.2) July 23, 2010Chapter 1: Hardware Design Using System Generatorce_clr Usage Recomme

System Generator for DSP User Guide www.xilinx.com 99UG640 (v 12.2) July 23, 2010Design Styles for the DSP48Design Styles for the DSP48About the DSP48