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26 DSP Selection Guide

Blackfin

TM

DSP Family

High Performance, Low Power Dual-MAC, 16-Bit Fixed-Point DSP

ADI’s new Blackfin DSP family is based on the

Micro Signal Architecture (MSA) jointly devel-

oped by ADI and the Intel Corporation. Blackfin

DSPs enable efficient processing of video, image,

and voice data by combining high-performance

signal processing functionality with the advan-

tages of a RISC microcontroller instruction set.

This unified programming model eliminates the

complexities traditionally associated with multi-

processor systems consisting of individual signal

and control processing elements.

Highly Parallel Computational Blocks

Computational blocks within the architecture are

designed to maximize the number of math oper-

ations that can execute within the same cycle.

The heart of the Blackfin DSP architecture is the

Data Arithmetic Unit that includes two 16-bit

Multiplier Accumulators (MACs), two 40-bit

Arithmetic Logic Units (ALUs), four 8-bit video

ALUs, and a single 40-bit barrel shifter. Each

MAC can perform a 16-bit by 16-bit multiply on

four independent data operands every cycle. The

40-bit ALUs can accumulate either two 40-bit

results or four 16-bit results. With this architec-

ture, 8-, 16- and 32-bit data word sizes can be

processed natively for maximum efficiency.

Flexible Addressing Capabilities

Blackfin DSPs provide efficient addressing of

data variables by supporting multiple address-

ing modes including indirect, auto-increment

and decrement, indexed, and bit reversed. Two

data address generators (DAG) provide

addresses for simultaneous dual operand fetch-

es from memory. The DAGs share a register

file that contains four sets of 32-bit index,

modify, length, and base registers useful for

implementing multiple circular buffers in inter-

nal or external memory. There are also eight

additional 32-bit registers – P0 through P5,

frame pointer, and stack pointer-- that can be

used as pointers for general indexing of vari-

ables and stack locations.

Hierarchical Memory

Blackfin DSPs support a hierarchical memory

model that expedites memory access to the core

for maximized throughput. The L1 memory is

connected directly to the core and operates at

full system clock speed. L2 memory, also oper-

ating at full system clock speed, is utilized for

accessing larger, bulk arrays of program and

data memory.

To provide for the performance needs of a DSP

and the programming ease of a RISC MCU, L1

memory can be configured as SRAM, cache, or

a combination of both. System designers can

map critical DSP data sets that require high

bandwidth and low latency into SRAM, while

maintaining the simple cache programming

model for microcontroller code.

The Memory Management Unit provides a

memory protection mechanism that, when cou-

pled with the core’s User and Supervisor modes,

can support a full OS Kernel, a feature not typi-

cally found on general-purpose DSPs.

SP

FP

P5

P4

P3

P2

P1

P0

I3

I2

I1

I0

L3

L2

L1

L0

B3

B2

B1

B0

M3

M2

M1

M0

DAG0 DAG1

R7

R6

R5

R4

R3

R2

R1

R0

16

8 8

40

Acc0

Barrel

Shifter

16

8 8

40

Acc1

Address Arithmetic Unit

Data Arithmetic Unit

Sequencer

Align

Decode

Loop Buffer

Control Unit

Core

Processor

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